1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a dynamic random access memory (DRAM) device based on a silicon on insulator (SOI) structure, and to a method for fabricating the same.
2. Background of the Related Art
Recently, processes for fabricating an integrated circuit device known as an SOI device have been developed. The SOI device is a semiconductor device fabricated within a thin silicon layer that covers an electrical insulating region formed on a substrate. The insulating region includes an SiO2 layer deposited on a semiconductor substrate, such as silicon or gallium arsenide. A circuit that is electrically insulated from a lower substrate can then be formed using the SOI device.
The SOI device provides various advantages as compared with a conventional semiconductor device. For example, the SOI device generally consumes less power. Also, the SOI device has smaller parasitic capacitance, and thus operates at higher speeds. Furthermore, since the SOI device is less susceptible to adverse effects of ionization emission, it is more reliable in applications where ionization emission may cause operational error.
Recently, a structure where devices are arranged on both sides of a SOI substrate to reduce an area of a unit cell has been disclosed. The SOI technology is used to mutually isolate active devices by forming the active devices within individual silicon islands supported on an upper portion of an insulating substrate. Accordingly, the SOI structure has excellent high packing density and reduces the number of process steps as compared with a bulk silicon structure. As described above, the active device formed on the upper portion of the SOI substrate is called an SOI device. Since the SOI device has a dramatically reduced parasitic capacitance as compared with a bulk silicon device, high operational speed of a circuit and low power consumption can be obtained.
Unwanted charges are accumulated in a bulk (region) while a unit cell is floating and operating, so that the concentration of impurities in the bulk is reduced. In this case, a so-called xe2x80x9cfloating bodyxe2x80x9d phenomenon, which varies a threshold value of a transistor, occurs. For this reason, a problem arises in that the unit cells do not operate uniformly.
A DRAM includes a memory cell array having a plurality of memory cells regularly arranged in X and Y directions, and a peripheral circuit formed around the memory cell array, for controlling the cells.
With an increase of packing density of a DRAM device, reduction of a unit cell area is required. It is becoming difficult to reduce a design rule of a unit cell due to limitation of photolithography process and degradation of electrical characteristic of a device. In this respect, many attempts to reduce an area of the unit cell in the same design rule by varying layout and sensing method of the cell have been made recently. Recently, to reduce the area of the unit cell, the SOI substrate has been used so that the devices are arranged at both sides of the SOI substrate.
A related art semiconductor device based on a SOI structure and method for fabricating the same will now be described with reference to the accompanying drawings.
As shown in FIGS. 1A and 1B, a DRAM device is formed on a SOI substrate 100 in which device isolation films 14 are formed. The SOI substrate, as shown in FIG. 1B, has a three-layered structure in which an SiO2 layer 12 is interposed between Si single crystallization structures. A lower silicon layer 11 acts as a mechanical support, and the SiO2 layer 12, which is an electrical insulating layer, and an ultra-thin single crystallization silicon layer 13 are formed thereon. A subminiature integrated circuit will be laid on the single crystallization silicon layer 13.
In case where a transistor is formed in a cell region and a peripheral region based on the SOI substrate, the applied voltage is small due to reduction of well and load resistance. For this reason, the transistor can operate at low power. Also, the transistor has high operational speed. However, when a bias is applied to the substrate to control a threshold voltage of the transistor of the cell region, a threshold voltage of the peripheral region also needs to be high. For this reason, it is difficult for the peripheral region circuits to realize low power consumption and high reproducibility. As high packing density is required in the DRAM device, a device can be formed within a semiconductor substrate formed over a handle wafer with an insulating material interposed between the sermiconductor substrate and the handle wafer. Thus, limitation on packing density in the process can be overcome. For this reason, much attention has been centered on fabrication of a DRAM device having an SOI structure. Further, as described above, in SOI transistors, the applied voltage is small due to reduction of well and load resistance. For this reason, the transistor can operate at low power and at high speed.
However,the DRAM device having a SOI structure has several problems. One of the problems is the xe2x80x9cfloating bodyxe2x80x9d effect. Since the active region of the transistor is electrically floating, the characteristics of the transistor are unstable, thereby causing malfunctions of the transistor and degradation of characteristics of the transistor.
Furthermore, in the SOI DRAM, to control the threshold voltage of the cell region, it is necessary to apply a substrate voltage. However, in the related semiconductor device based on an SOI structure, a substrate voltage is applied to the peripheral region as well as the cell region, thereby degrading the low pow-r characteristic and high reproducibility of the SOI device.
Accordingly, the present invention is directed to a semiconductor device having recessed SOI structure and a method for fabricating same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The inventions solves at least the above problems and/or disadvantages and provides at least the advantages described hereinafter.
An aspect of the present invention is to provide a semiconductor device having a recessed SOI structure and method for fabricating the same in which a substrate voltage is applied to a cell region to easily control a threshold voltage, and where a peripheral region is recessed to realize low power and high reproducibility.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description or its equivalents and claims hereof as well as the appended drawings.
To achieve at least these advantages in a whole or in part and in accordance with purposes of the present invention, as embodied and broadly described, a semiconductor device having a recessed silicon on insulator (SOI) structure includes an SOI substrate having a cell region, a peripheral region and a field region, the SOI substrate having a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, a trench in the field region of the second semiconductor layer, a device isolation film within the trench, a peripheral region recessed in the second semiconductor layer, and an active semiconductor device on the cell region and the peripheral region of the second semiconductor layer.
In another aspect, a method for fabricating a semiconductor device based on a SOI structure having an SOI substrate including a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the insulating layer, the semiconductor device having a cell region, a peripheral region and a field region, the method includes the steps of forming a field insulating film within the second semiconductor layer of the peripheral region and on a surface of the second semiconductor layer, forming a trench in the field region of the second semiconductor layer, forming a device isolation film within the trench, and removing the field insulating film to form a recessed peripheral region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.